US 12,445,038 B2
Turn on delay measurements for capacitive load
Vasishta Kidambi, Hyderabad (IN); Harsh Patel, Mumbai (IN); Aalok Dyuti Saha, Bangalore (IN); and Subrato Roy, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Aug. 19, 2022, as Appl. No. 17/891,456.
Claims priority of application No. 202141038083 (IN), filed on Aug. 23, 2021.
Prior Publication US 2023/0072953 A1, Mar. 9, 2023
Prior Publication US 2024/0283350 A9, Aug. 22, 2024
Int. Cl. G01R 31/28 (2006.01); H02M 1/08 (2006.01)
CPC H02M 1/08 (2013.01) [G01R 31/2882 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A testing method comprising:
connecting a capacitor having a first capacitance to an output terminal of an integrated circuit (IC);
generating a pulse signal responsive to an enable signal provided at at least one input terminal of the IC;
measuring a no-load delay representative of a time difference between a start of the enable signal and a start of the pulse signal;
providing a drive signal to the output terminal to cause a linearly increasing voltage across the capacitor responsive to the pulse signal;
measuring the linearly increasing voltage at the output terminal responsive to the drive signal;
determining a first capacitance charge time for the capacitor responsive to the linearly increasing voltage reaching a threshold; and
determining a second capacitance charge delay for a second capacitance based on the first capacitance charge time and the no-load delay.