US 12,444,727 B2
Semiconductor package structure and manufacturing method
Xiaofei Sun, Hefei (CN); and Changhao Quan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Filed on Jan. 10, 2023, as Appl. No. 18/152,188.
Application 18/152,188 is a continuation of application No. PCT/CN2022/110253, filed on Aug. 4, 2022.
Claims priority of application No. 202210853472.6 (CN), filed on Jul. 8, 2022.
Prior Publication US 2024/0014196 A1, Jan. 11, 2024
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/36 (2006.01); H01L 23/42 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 23/36 (2013.01); H01L 23/42 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 25/0652 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package structure, comprising:
a first package structure, comprising an intermediary layer and a molding compound, wherein a plurality of first connection pads are disposed on the intermediary layer, and the molding compound wraps the intermediary layer and is coplanar to the plurality of first connection pads; and
a second package structure, disposed on the intermediary layer and electrically connected to the plurality of first connection pads,
wherein a gap is formed between the first package structure and the second package structure;
wherein the first package structure further comprises:
a base plate;
at least one first chip stack body, disposed on the base plate; and
at least one second chip stack body, disposed on the base plate and spaced apart from the first chip stack body,
wherein the intermediary layer is disposed on the first chip stack body and the second chip stack body:
wherein the first chip stack body comprises one first chip, and the second chip stack body comprises one second chip; and
wherein the first chip is electrically connected to the second chip by means of the intermediary layer.