US 12,444,716 B2
Light-emitting diode device
Shiou-Yi Kuo, Hsinchu (TW); Te-Chung Wang, Hsinchu (TW); and Guo-Yi Shiu, Hsinchu (TW)
Assigned to LEXTAR ELECTRONICS CORPORATION, Hsinchu (TW)
Filed by Lextar Electronics Corporation, Hsinchu (TW)
Filed on Mar. 17, 2023, as Appl. No. 18/185,531.
Claims priority of provisional application 63/321,790, filed on Mar. 21, 2022.
Claims priority of application No. 111134657 (TW), filed on Sep. 14, 2022.
Prior Publication US 2023/0299056 A1, Sep. 21, 2023
Int. Cl. H01L 25/075 (2006.01); H01L 25/16 (2023.01); H01L 27/12 (2006.01); H01L 33/10 (2010.01); H01L 33/62 (2010.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10H 20/814 (2025.01); H10H 20/857 (2025.01)
CPC H01L 25/0753 (2013.01) [H01L 25/167 (2013.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01); H10H 20/814 (2025.01); H10H 20/857 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A light-emitting diode device, comprising:
a pixel structure, comprising:
a first light-emitting diode chip having a first top surface;
a second light-emitting diode chip having a second top surface;
a third light-emitting diode chip, having a light-emitting surface and a third top surface opposite to each other; wherein the first light-emitting diode chip and the second light-emitting diode chip are arranged side by side on the third top surface, the first light-emitting diode chip has a first vertical projection on the third top surface, the second light-emitting diode chip has a second vertical projection on the third top surface, and the first vertical projection and the second vertical projection do not overlap each other;
a passivation layer covering the first light-emitting diode chip, the second light-emitting diode chip and the third light-emitting diode chip; and
a first circuit layer, a second circuit layer, a third circuit layer and a fourth circuit layer separated from each other and located between the third light-emitting diode chip and the passivation layer; wherein the first circuit layer has a first bonding surface, the second circuit layer has a second bonding surface, the third circuit layer has a third bonding surface, and the fourth circuit layer has a fourth bonding surface, and wherein the passivation layer has openings, the openings respectively correspond to and are located on the first bonding surface of the first circuit layer, the second bonding surface of the second circuit layer, the third bonding surface of the third circuit layer and the fourth bonding surface of the fourth circuit layer; wherein vertical projections of the first bonding surface and the second bonding surface on the third top surface respectively overlap the first vertical projection and are separated from the second vertical projection, and vertical projections of the third bonding surface and the fourth bonding surface on the third top surface respectively overlap the second vertical projection and are separated from the first vertical projection.