US 12,444,715 B2
Semiconductor package structure
Yi-Lin Tsai, Hsinchu (TW); Wen-Sung Hsu, Hsin-Chu (TW); I-Hsuan Peng, Hsinchu (TW); and Yi-Jou Lin, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MediaTek Inc., Hsin-Chu (TW)
Filed on Oct. 18, 2023, as Appl. No. 18/489,814.
Application 18/489,814 is a division of application No. 17/208,198, filed on Mar. 22, 2021, granted, now 11,830,851.
Claims priority of provisional application 63/006,150, filed on Apr. 7, 2020.
Prior Publication US 2024/0047427 A1, Feb. 8, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H01L 23/498 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/18 (2013.01); H01L 23/49822 (2013.01); H01L 2224/13009 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73253 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06548 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor package structure, comprising:
a substrate;
a redistribution layer over the substrate and having a first surface and a second surface opposite to the first surface;
a plurality of first bump structures on the first surface of the redistribution layer and electrically coupling the redistribution layer to a wiring structure of the substrate;
a first semiconductor component on the first surface of the redistribution layer and adjacent to the plurality of first bump structures;
a first passivation layer on the first semiconductor component;
a plurality of first conductive vias in the first passivation layer and electrically coupled to the first semiconductor component;
a plurality of second bump structures between the redistribution layer and the first conductive vias and directly connecting the redistribution layer and the first conductive vias;
a second semiconductor component on the second surface of the redistribution layer; and
a first underfill material that surrounds the plurality of first bump structures, wherein the first underfill material is in direct contact with a top surface of a first portion of the substrate and exposes a top surface of a second portion of the substrate, wherein the top surface of the first portion of the substrate is substantially level with the top surface of the second portion of the substrate,
wherein the second semiconductor component is electrically coupled to the first semiconductor component through the redistribution layer, and is electrically coupled to the wiring structure of the substrate through the plurality of first bump structures.