US 12,444,714 B2
Semiconductor structure
Hsien-Wei Chen, Hsinchu (TW); Jie Chen, New Taipei (TW); Ming-Fa Chen, Taichung (TW); and Ching-Jung Yang, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 22, 2023, as Appl. No. 18/472,246.
Application 17/246,692 is a division of application No. 16/441,017, filed on Jun. 14, 2019, granted, now 10,998,293, issued on May 4, 2021.
Application 18/472,246 is a continuation of application No. 17/246,692, filed on May 2, 2021, granted, now 11,837,579.
Prior Publication US 2024/0014181 A1, Jan. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2224/0224 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80125 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06593 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first die, comprising a first interconnect structure and a first active pad electrically connected to the first interconnect structure; a first active bonding via, wherein the first active pad has a first surface facing the first interconnect structure and a second surface opposite to the first surface, the first active bonding via has a third surface facing the first interconnect structure and a fourth surface opposite to the third surface, and the second surface of the first active pad is disposed between the third surface and the fourth surface of the first active bonding via; and
a first bonding dielectric layer, covering the second surface of the first active pad and laterally encapsulating sidewalls of the first active pad and the first active bonding via, wherein the first bonding dielectric layer is a single layer.