US 12,444,713 B2
Semiconductor assemblies with hybrid fanouts and associated methods and systems
Bharat Bhushan, Taichung (TW); Pratap Murali, Meridian, ID (US); and Raj K. Bansal, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Sep. 13, 2023, as Appl. No. 18/367,866.
Application 17/850,992 is a division of application No. 17/103,486, filed on Nov. 24, 2020, granted, now 11,450,645, issued on Sep. 20, 2022.
Application 18/367,866 is a continuation of application No. 17/850,992, filed on Jun. 27, 2022, granted, now 11,769,756.
Prior Publication US 2024/0088100 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3185 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/85 (2013.01); H01L 24/92 (2013.01); H01L 25/50 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/9222 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first semiconductor die comprising a conductive trace coupled with a first conductive bump at a bottom surface of the first semiconductor die;
a molding coupled with a lateral edge of the first semiconductor die, wherein the molding comprises a via coupled with a conductive pad that is positioned at a first side of the molding, the first side of the molding corresponding to the bottom surface of the first semiconductor die, wherein the conductive pad is coupled with a second conductive bump;
a second semiconductor die coupled with the first semiconductor die on a top surface, opposite the bottom surface, of the first semiconductor die, wherein the second semiconductor die comprises a bond pad; and
a bond wire directly coupling the bond pad of the second semiconductor die and the via of the molding.
 
10. An apparatus, comprising:
a first semiconductor die comprising a conductive trace coupled with a first conductive bump at a bottom surface of the first semiconductor die;
a molding coupled with a lateral edge of the first semiconductor die, wherein the molding comprises a via coupled with a conductive pad that is positioned at a first side of the molding, the first side of the molding corresponding to the bottom surface of the first semiconductor die, wherein the conductive pad is coupled with a second conductive bump;
a second semiconductor die coupled with the first semiconductor die on a top surface, opposite the bottom surface, of the first semiconductor die, wherein the second semiconductor die comprises a bond pad;
a bond wire directly coupling the bond pad of the second semiconductor die and the via of the molding; and
a circuit board coupled with the first conductive bump and the second conductive bump.
 
18. An apparatus, comprising:
a first semiconductor die comprising a conductive trace coupled with a first conductive bump at a bottom surface of the first semiconductor die;
a molding coupled with a lateral edge of the first semiconductor die, wherein the molding comprises a through-mold via (TMV) coupled with a conductive pad that is positioned at a first side of the molding, the first side of the molding corresponding to the bottom surface of the first semiconductor die, wherein the conductive pad is coupled with a second conductive bump;
a second semiconductor die coupled with the first semiconductor die on a top surface, opposite the bottom surface, of the first semiconductor die, wherein the second semiconductor die comprises a bond pad;
a bond wire directly coupling the bond pad of the second semiconductor die and the TMV of the molding; and
a printed circuit board (PCB) coupled with the first conductive bump and the second conductive bump.