US 12,444,709 B2
Overlapping die stacks for NAND package architecture
Enyong Tai, Singapore (SG); Hem P. Takiar, Fremont, CA (US); Li Wang, Singapore (SG); and Hong Wan Ng, Singapore (SG)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 18, 2024, as Appl. No. 18/416,180.
Application 18/416,180 is a continuation of application No. 17/723,386, filed on Apr. 18, 2022, granted, now 11,908,833.
Application 17/723,386 is a continuation of application No. 17/003,789, filed on Aug. 26, 2020, granted, now 11,309,281, issued on Apr. 19, 2022.
Prior Publication US 2024/0153912 A1, May 9, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/0652 (2013.01) [H01L 24/45 (2013.01); H01L 24/85 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2225/06562 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor assembly, comprising:
a substrate including external connections;
a first stack of semiconductor dies disposed over a first location on the substrate and having a first height;
a second stack of semiconductor dies disposed over a second location on the substrate and having a second height different than the first height; and
a controller die disposed on the substrate between the first stack and second stack;
wherein the first stack includes an uppermost semiconductor die of the first stack, the second stack includes an uppermost semiconductor die of the second stack, and at least a portion of the uppermost semiconductor die of the second stack is superimposed above at least a portion of the uppermost semiconductor die of the first stack such that the semiconductor die of the second stack is not physically supported by the first stack, and
wherein the portion of the uppermost semiconductor die of the second stack and the portion of the uppermost semiconductor die of the first stack are both superimposed over the controller die.