US 12,444,708 B2
Semiconductor package including stacked semiconductor chips
Jong Joo Lee, Icheon-si (KR); and Kyeong Min Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 27, 2022, as Appl. No. 17/730,715.
Claims priority of application No. 10-2021-0149671 (KR), filed on Nov. 3, 2021.
Prior Publication US 2023/0139378 A1, May 4, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/3201 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/3303 (2013.01); H01L 2224/48011 (2013.01); H01L 2224/48148 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1438 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a substrate having a first side and a second side, the first and second sides being on opposite sides of the substrate in a first direction;
a first semiconductor chip disposed over the substrate;
a first one-side third semiconductor chip stack disposed over the substrate and spaced apart from the first semiconductor chip, the first one-side third semiconductor chip stack being closer to the first side than the first semiconductor chip;
a second semiconductor chip stack disposed over the first semiconductor chip and the first one-side third semiconductor chip stack, the second semiconductor chip stack including at least two second semiconductor chips; and
a second one-side third semiconductor chip stack disposed over the second semiconductor chip stack;
wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack includes a plurality of third semiconductor chips that are offset-stacked, offset towards the first side as the plurality of third semiconductor chips are farther from the substrate, so that chip pads that are disposed on other-side edge regions of the plurality of the third semiconductor chips are exposed;
wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack is electrically connected to the substrate through a bonding wire that extends to the substrate while connecting the chip pads of the plurality of third semiconductor chips to each other;
wherein the second semiconductor chip stack includes a volatile memory;
wherein each of the first one-side third semiconductor chip stack and the second one-side third semiconductor chip stack includes a non-volatile memory; and
wherein the first semiconductor chip includes a memory controller.