US 12,444,700 B2
Semiconductor device, semiconductor package, and memory system
Kwangsook Noh, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 26, 2022, as Appl. No. 17/973,731.
Claims priority of application No. 10-2021-0157518 (KR), filed on Nov. 16, 2021.
Prior Publication US 2023/0154871 A1, May 18, 2023
Int. Cl. H01L 23/64 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/645 (2013.01) [H01L 23/481 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/14335 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/30107 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an element region including a semiconductor substrate and a plurality of elements formed on the semiconductor substrate; and
a wiring region disposed on the element region and including an interlayer insulating layer, a plurality of wiring patterns in the interlayer insulating layer, and a via structure extending in a first direction in the interlayer insulating layer, the first direction being perpendicular to an upper surface of the semiconductor substrate, wherein
the plurality of elements includes a first input/output (I/O) circuit transmitting and receiving a first signal and a second I/O circuit transmitting and receiving a second signal, different from the first signal,
the plurality of wiring patterns includes a coil pattern providing an inductor circuit,
the coil pattern is connected to the first I/O circuit, and
the via structure passes through a center of the coil pattern and is connected to the second I/O circuit.