US 12,444,698 B1
Electronic component-mounting substrate and electronic device
Tamaki Matsuo, Chuo-ku (JP); Kazunori Matsudo, Chuo-ku (JP); Kenji Ando, Chuo-ku (JP); and Wataru Endo, Chuo-ku (JP)
Assigned to artience Co., Ltd., Tokyo (JP); and TOYOCHEM CO., LTD., Tokyo (JP)
Appl. No. 18/880,591
Filed by artience Co., Ltd., Tokyo (JP); and TOYOCHEM CO., LTD., Tokyo (JP)
PCT Filed Mar. 27, 2024, PCT No. PCT/JP2024/012467
§ 371(c)(1), (2) Date Feb. 26, 2025,
PCT Pub. No. WO2025/115245, PCT Pub. Date Jun. 5, 2025.
Claims priority of application No. 2023-202349 (JP), filed on Nov. 30, 2023.
Int. Cl. H01L 23/00 (2006.01); B32B 7/06 (2019.01)
CPC H01L 23/562 (2013.01) [B32B 7/06 (2013.01); B32B 2307/7376 (2023.05); B32B 2457/14 (2013.01)] 8 Claims
OG exemplary drawing
 
1. An electronic component-mounting substrate comprising:
a substrate;
an electronic component mounted on at least one surface of the substrate; and
a peeling or falling prevention layer that coats the substrate and the electronic component, wherein
the peeling or falling prevention layer satisfies both the following (1) and (2):
(1) a rate of change X of a coefficient of static friction obtained in the following [Formula 1] is −50% or greater and 200% or smaller:
X=(μk300−μk100)/μk100×100  [Formula 1]
wherein μk100 is a coefficient of static friction at a 100-th reciprocating wear test of the peeling or falling prevention layer, and μk300 is a coefficient of static friction at a 300-th reciprocating wear test of the peeling or falling prevention layer; and
(2) an index Y obtained in the following [Formula 2] is 0.8 or greater and 20.0 or smaller:
Y=R2/(R1+A1)  [Formula 2]
wherein R1 is a radius of curvature of a curved surface of a corner part of the electronic component in a cross section of the electronic component-mounting substrate, R2 is a radius of curvature of a corner part of the peeling or falling prevention layer in the cross section of the electronic component-mounting substrate, and A1 is a thickness of the corner part of the peeling or falling prevention layer in the cross section of the electronic component-mounting substrate.