US 12,444,697 B2
Semiconductor device
Noh Yeong Park, Suwon-si (KR); Beomjin Park, Hwaseong-si (KR); Dong Il Bae, Seongnam-si (KR); Sangwon Baek, Hwaseong-si (KR); and Hyun-Seung Song, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 21, 2024, as Appl. No. 18/612,304.
Application 18/612,304 is a continuation of application No. 17/352,503, filed on Jun. 21, 2021, granted, now 11,961,806.
Claims priority of application No. 10-2020-0166044 (KR), filed on Dec. 1, 2020.
Prior Publication US 2024/0234343 A1, Jul. 11, 2024
Int. Cl. H10D 30/01 (2025.01); H01L 21/02 (2006.01); H01L 23/00 (2006.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H01L 23/562 (2013.01) [H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate including a first region and a second region;
a first active pattern on the first region, the first active pattern comprising a pair of first source/drain patterns and a first channel pattern therebetween, the first channel pattern comprising a plurality of first semiconductor patterns stacked on the substrate;
a first gate electrode provided on the first channel pattern; and
a supporting pattern being configured to connect the plurality of first semiconductor patterns therebetween, wherein the supporting pattern is separated from each of the pair of first source/drain patterns.