US 12,444,696 B2
Package structure
Chia-Kuei Hsu, Hsinchu (TW); Ming-Chih Yew, Hsinchu (TW); Shu-Shen Yeh, Taoyuan (TW); Che-Chia Yang, Taipei (TW); Po-Yao Lin, Zhudong Township (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 28, 2023, as Appl. No. 18/520,971.
Application 18/520,971 is a continuation of application No. 17/350,351, filed on Jun. 17, 2021, granted, now 11,855,004.
Prior Publication US 2024/0096822 A1, Mar. 21, 2024
Int. Cl. H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/3512 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a first conductive pad in a first insulating layer;
a conductive via in a second insulating layer directly under the first conductive pad; and
a first under bump metallurgy structure directly under the first conductive via, wherein:
in a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and
in a cross-sectional view, a width of the first conductive pad is greater than a width of the first under bump metallurgy structure.