US 12,444,695 B2
Memory device including support structures and contact structures having different materials
Shuangqiang Luo, Boise, ID (US); and John Hopkins, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 14, 2022, as Appl. No. 17/694,040.
Prior Publication US 2023/0290739 A1, Sep. 14, 2023
Int. Cl. H01L 23/52 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01)
CPC H01L 23/562 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53257 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10D 30/6892 (2025.01); H10D 30/696 (2025.01); H10D 64/035 (2025.01); H10D 64/037 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
tiers located one over another, the tiers including respective memory cells and control gates for the memory cells;
a first pillar extending through the tiers and separated from the control gates, the first pillar including a first dielectric liner portion and a first core portion adjacent the first dielectric liner portion, the first dielectric liner portion and the first core portion extending along a length of the first pillar; and
a second pillar extending through the tiers and separated from the control gates, the second pillar including a second dielectric liner portion and a second core portion adjacent the second dielectric liner portion, the second dielectric portion and the second core portion extending along a length of the second pillar, wherein the first core portion and the second core portion have different materials.