US 12,444,689 B2
Semiconductor package and method of manufacturing the same
Sheng-Ming Wang, Kaohsiung (TW); Tien-Szu Chen, Kaohsiung (TW); Wen-Chih Shen, Kaohsiung (TW); Hsing-Wen Lee, Kaohsiung (TW); and Hsiang-Ming Feng, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on Feb. 6, 2024, as Appl. No. 18/434,711.
Application 18/434,711 is a continuation of application No. 17/109,111, filed on Dec. 1, 2020, granted, now 11,894,308.
Application 17/109,111 is a continuation of application No. 16/109,272, filed on Aug. 22, 2018, granted, now 10,854,550.
Claims priority of provisional application 62/564,939, filed on Sep. 28, 2017.
Prior Publication US 2024/0213168 A1, Jun. 27, 2024
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/66 (2006.01); H01L 25/065 (2023.01); H01P 3/06 (2006.01)
CPC H01L 23/5386 (2013.01) [H01L 21/4857 (2013.01); H01L 21/6835 (2013.01); H01L 23/3107 (2013.01); H01L 23/3677 (2013.01); H01L 23/5383 (2013.01); H01L 23/66 (2013.01); H01P 3/06 (2013.01); H01L 23/3128 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2223/6622 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73253 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06558 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19103 (2013.01); H01L 2924/19105 (2013.01); H05K 2201/09854 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a dielectric layer, having a first surface and a second surface opposite to the first surface;
a first conductive via and a second conductive via extending between the first surface and the second surface, the first conductive via comprising a first pattern, the second conductive via comprising a second pattern; and
a die bonded to a substrate, wherein a vertical projection of the first conductive via is not overlapped with a vertical projection of the die from a top view;
wherein the first pattern comprises at least two first geometric centers corresponding to at least two first geometric patterns, respectively, and wherein the second pattern comprises at least two second geometric centers corresponding to at least two second geometric patterns, respectively, and wherein a first imaginary line connecting the at least two first geometric centers is non-parallel to a second imaginary line connecting the at least two second geometric centers,
wherein the at least two first geometric patterns comprises a first number of geometric patterns, the at least two second geometric patterns comprises a second number of geometric patterns more than the first number of geometric patterns.