US 12,444,688 B2
Deep trench protection
Fu-Chiang Kuo, Hsinchu (TW); Tao-Cheng Liu, Hsinchu (TW); Shih-Chi Kuo, Taipei (TW); and Tsung-Hsien Lee, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jun. 15, 2022, as Appl. No. 17/841,526.
Application 17/065,979 is a division of application No. 15/904,013, filed on Feb. 23, 2018, granted, now 10,804,206.
Application 17/841,526 is a continuation of application No. 17/065,979, filed on Oct. 8, 2020, granted, now 11,373,952.
Claims priority of provisional application 62/539,038, filed on Jul. 31, 2017.
Prior Publication US 2022/0310520 A1, Sep. 29, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/5384 (2013.01) [H01L 21/76229 (2013.01); H01L 21/76843 (2013.01); H01L 21/78 (2013.01); H01L 23/53266 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a first dielectric layer overlaying the substrate;
a second dielectric layer overlaying the first dielectric layer;
a trench structure extending through the first dielectric layer and the second dielectric layer;
a protection layer over the trench structure along an interface between the first dielectric layer and the second dielectric layer, wherein the protection layer is formed over an entirety of a sidewall of the trench structure, the sidewall of the trench structure extending through the first and second dielectric layers and into the substrate, wherein the entirety of the sidewall of the trench structure is flat and inclined, and wherein a top portion of the trench structure is wider than a bottom portion of the trench structure; and
a singulation sidewall that cuts through the protection layer and the substrate, wherein the singulation sidewall is defined at least in part by a sidewall of the substrate and a lower segment of a first sidewall of the protection layer that are aligned with one another, wherein an upper segment of the first sidewall is slanted relative to the lower segment and has a height greater than a height of the lower segment; and
wherein the second dielectric layer is a top most dielectric layer of the semiconductor device and no portions of a top surface of the second dielectric layer has the protection layer disposed thereon.