US 12,444,686 B2
Semiconductor device
Junichi Koike, Miyagi (JP); Masataka Yahagi, Miyagi (JP); and Yuki Yamada, Miyagi (JP)
Assigned to TOHOKU UNIVERSITY, Sendai (JP)
Appl. No. 17/928,428
Filed by Tohoku University, Miyagi (JP)
PCT Filed Jun. 4, 2020, PCT No. PCT/JP2020/022202
§ 371(c)(1), (2) Date Nov. 29, 2022,
PCT Pub. No. WO2021/245893, PCT Pub. Date Dec. 9, 2021.
Prior Publication US 2023/0154851 A1, May 18, 2023
Int. Cl. H01L 23/532 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/53238 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, which has a wiring structure including an insulating layer, a conductive wiring, and a diffusion barrier layer disposed between the insulating layer and the conductive wiring in a manner of being in contact with both the insulating layer and the conductive wiring, wherein
the insulating layer contains a silicon oxide and/or a silicon oxide containing at least one element of C, N, and H,
the conductive wiring contains Cu and/or Co,
the diffusion barrier layer is made of an alloy having an amorphous structure containing a first metal and a second element in an amount of 90% by mass or more in total,
the first metal is any one selected from Co, Ru, and Mo,
wherein when the first metal is Co, the second element is one or two or more selected from Al, and Nb,
wherein when the first metal is Ru, the second element is Zr, and
wherein when the first metal is Mo, the second element is one or two selected from Y and B.