US 12,444,685 B2
Backside electrical contact for PMOS epitaxial voltage supply
Clifford Ong, Portland, OR (US); Zheng Guo, Portland, OR (US); Eirc A. Karl, Portland, OR (US); Smita Shridharan, Beaverton, OR (US); Mauro J. Kobrinsky, Portland, OR (US); Shem O. Ogadhoh, Beaverton, OR (US); Clifford J. Engel, Hillsboro, OR (US); Charles H. Wallace, Portland, OR (US); and Leonard P. Guler, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 31, 2022, as Appl. No. 17/710,867.
Prior Publication US 2023/0317612 A1, Oct. 5, 2023
Int. Cl. H10D 84/85 (2025.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 10/00 (2023.01)
CPC H01L 23/5286 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 10/12 (2023.02); H10B 10/125 (2023.02); H10D 84/85 (2025.01); H10D 84/853 (2025.01)] 25 Claims
OG exemplary drawing
 
1. A transistor comprising:
a backside contact metal;
a first epitaxial layer on a first backside contact metal, wherein the first backside contact metal is directly electrically coupled with the first epitaxial layer, and wherein the first epitaxial layer is part of an NMOS;
a second epitaxial layer on a second backside contact metal, wherein the second backside contact metal is electrically coupled with the second epitaxial layer, and wherein the second epitaxial layer is part of a PMOS; and
wherein the first backside contact metal is electrically coupled with a voltage ground (VSS), and wherein the second backside contact metal is electrically coupled with the SRAM VCC power supply (SVCC).