US 12,444,678 B2
Spacer-based self-aligned interconnect features
Moshe Dolejsi, Portland, OR (US); Travis W. Lajoie, Forest Grove, OR (US); and Abhishek Anil Sharma, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 11, 2022, as Appl. No. 17/692,346.
Prior Publication US 2023/0290726 A1, Sep. 14, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01)
CPC H01L 23/528 (2013.01) [H01L 21/76834 (2013.01); H01L 21/76897 (2013.01); H10B 12/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first conductive structure and a second conductive structure;
a first spacer and a second spacer each comprising a first dielectric material;
a layer comprising a second dielectric material that is compositionally different from the first dielectric material;
a first interconnect feature above and at least partially landed on the first conductive structure, wherein the first interconnect feature is laterally between the first spacer and the second spacer; and
a second interconnect feature above and at least partially landed on the second conductive structure, wherein the second interconnect feature is laterally between the second spacer and the layer comprising the second dielectric material.