US 12,444,676 B2
Self-aligned via for interconnect structure
Chieh-Han Wu, Kaohsiung (TW); Cheng-Hsiung Tsai, Miaoli County (TW); Chih Wei Lu, Hsinchu (TW); and Chung-Ju Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 17, 2024, as Appl. No. 18/745,773.
Application 18/745,773 is a continuation of application No. 18/301,447, filed on Apr. 17, 2023, granted, now 12,046,551.
Application 18/301,447 is a continuation of application No. 17/671,394, filed on Feb. 14, 2022, granted, now 11,631,639, issued on Apr. 18, 2023.
Application 17/671,394 is a continuation of application No. 16/572,683, filed on Sep. 17, 2019, granted, now 11,251,118, issued on Feb. 15, 2022.
Prior Publication US 2024/0339396 A1, Oct. 10, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76816 (2013.01); H01L 21/76829 (2013.01); H01L 21/76843 (2013.01); H01L 21/7685 (2013.01); H01L 23/53209 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 24/32 (2013.01); H01L 24/37 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An interconnect structure comprising:
a substrate;
a glue layer over the substrate;
a first conductive line disposed on a first portion of the glue layer;
a first portion of a conductive etch stop layer (ESL) disposed on the first conductive line; and
a barrier layer extending continuously along a sidewall of the first portion of the glue layer, a sidewall of the first conductive line, a sidewall of the first portion of the conductive ESL, and a top surface of the first portion of the conductive ESL.