US 12,444,675 B2
Semiconductor devices
Euibok Lee, Seoul (KR); Rakhwan Kim, Suwon-si (KR); Wandon Kim, Seongnam-Si (KR); Sunyoung Noh, Hwaseong-si (KR); and Hanmin Jang, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 27, 2022, as Appl. No. 17/705,343.
Claims priority of application No. 10-2021-0088976 (KR), filed on Jul. 7, 2021.
Prior Publication US 2023/0011088 A1, Jan. 12, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 23/5283 (2013.01); H01L 23/53209 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a lower structure including a substrate;
a first interconnection layer extending lengthwise in a first direction on the lower structure, and including a first metal;
a first via contacting a portion of an upper surface of the first interconnection layer and including a second metal different from the first metal;
a second via contacting at least a portion of an upper surface of the first via and having a maximum width narrower than a maximum width of the first via; and
a second interconnection layer connected to the second via and extending lengthwise in a second direction, perpendicular to the first direction,
wherein the first interconnection layer has inclined side surfaces in which a width of the first interconnection layer becomes narrower towards an upper region of the first interconnection layer, and
wherein the first via has inclined side surfaces in which a width of the first via becomes narrower towards an upper region of the first via.