	US 12,444,674 B2
	Back-end-of-line passive device structure
Tsung-Chieh Hsiao, Changhua County (TW); Hsiang-Ku Shen, Hsinchu (TW); Yuan-Yang Hsiao, Hsinchu (TW); Chen-Chiu Huang, Hsinchu (TW); and Dian-Hau Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/447,722.
Application 18/447,722 is a division of application No. 17/586,287, filed on Jan. 27, 2022, granted, now 11,990,401.
Claims priority of provisional application 63/285,820, filed on Dec. 3, 2021.
Prior Publication US 2023/0386996 A1, Nov. 30, 2023
Int. Cl. H01L 23/522 (2006.01); H10D 1/00 (2025.01); H10D 1/68 (2025.01)

CPC H01L 23/5223 (2013.01) [H10D 1/696 (2025.01); H10D 1/714 (2025.01); H10D 1/716 (2025.01)]

20 Claims

1. A device structure, comprising:

a passivation layer;

a first conductor plate layer disposed on the passivation layer;

a first insulator layer over the first conductor plate layer;

a second conductor plate layer disposed over the first insulator layer;

a second insulator layer over the second conductor plate layer;

a third conductor plate layer disposed over the second insulator layer and wrapping over edges of the second conductor plate layer;

a third insulator layer over the third conductor plate layer; and

a fourth conductor plate layer disposed over the third insulator layer,

wherein a vertical projection area of the fourth conductor plate layer falls completely in a vertical projection area of the third conductor plate layer.

12. A device structure, comprising:

a passivation layer;

a first conductor plate layer disposed on the passivation layer;

a second conductor plate layer disposed over the first conductor plate layer;

a third conductor plate layer disposed over the second conductor plate layer; and

a fourth conductor plate layer disposed over the third conductor plate layer,

wherein a vertical projection area of an outer edge of the second conductor plate layer falls completely within a vertical projection area of an outer edge of the first conductor plate layer,

wherein a vertical projection area of an outer edge of the fourth conductor plate layer falls completely within a vertical projection area of an outer edge of the third conductor plate layer.

17. A device structure, comprising:

a first passivation layer;

a first conductor plate layer disposed on the first passivation layer;

a second conductor plate layer disposed over the first conductor plate layer;

a third conductor plate layer disposed over the second conductor plate layer;

a fourth conductor plate layer disposed over the third conductor plate layer;

a second passivation layer disposed over the fourth conductor plate layer;

a first dummy pad, a second dummy pad disposed over the first dummy pad, and a third dummy pad disposed over the second dummy pad; and

a contact via extending through the first passivation layer, the first conductor plate layer, the second conductor plate layer, the third conductor plate layer, the fourth conductor plate layer, and the second passivation layer,

wherein the contact via further extends through the first dummy pad, the second dummy pad and the third dummy pad,

wherein a vertical projection area of an outer edge of the third dummy pad falls completely within a vertical projection area of an outer edge of the second dummy pad,

wherein a vertical projection area of an outer edge of the first dummy pad falls completely within the vertical projection area of the outer edge of the second dummy pad.