US 12,444,672 B2
Hybrid bonding technologies with thermal expansion compensation structures
Jeremy Ecton, Gilbert, AZ (US); Aleksandar Aleksov, Chandler, AZ (US); Hiroki Tanaka, Gilbert, AZ (US); Brandon Marin, Gilbert, AZ (US); Srinivas Pietambaram, Chandler, AZ (US); and Xavier Brun, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 30, 2022, as Appl. No. 17/957,751.
Prior Publication US 2024/0113005 A1, Apr. 4, 2024
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01)
CPC H01L 23/49833 (2013.01) [H01L 21/4803 (2013.01); H01L 21/481 (2013.01); H01L 21/4846 (2013.01); H01L 23/13 (2013.01); H01L 23/49894 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 24/16 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/1624 (2013.01); H01L 2224/80201 (2013.01); H01L 2224/80379 (2013.01); H01L 2924/0665 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit package structure, comprising:
a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure; and
a cavity in a surface of the first substrate, wherein the cavity is adjacent to the conductive interconnect structure, and wherein a portion of the dielectric material is within a first portion of the cavity and a second portion of the cavity is free of the dielectric material.