US 12,444,664 B2
Loading frame for high I/O count packaged semiconductor chip
Jeffory L. Smalley, Olympia, WA (US); Mohanraj Prabhugoud, Hillsboro, OR (US); Steven A. Klein, Chandler, AZ (US); and Mengqi Liu, Hillsboro, OR (US)
Assigned to SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed by SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/132,391.
Prior Publication US 2021/0183737 A1, Jun. 17, 2021
Int. Cl. H01L 23/40 (2006.01); H01L 23/495 (2006.01)
CPC H01L 23/4006 (2013.01) [H01L 23/49544 (2013.01); H01L 23/49551 (2013.01); H01L 23/49568 (2013.01); H01L 2023/405 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a packaged semiconductor chip;
a socket;
a heat sink for the packaged semiconductor chip; and
a loading frame for mounting the packaged semiconductor chip and the heat sink to the socket, wherein the loading frame comprises a loading frame base coupled to at least one frame leg, and wherein the at least one frame leg comprises metal folded inward on an edge of the at least one frame leg to form a C shaped cross section.