US 12,444,660 B2
Test structure for void and topography monitoring in a flash memory device
Ken-Ying Liao, Tainan (TW); Chih-Wei Sung, Kaohsiung (TW); Tzu-Pin Lin, Tainan (TW); Huai-jen Tung, Tainan (TW); Po-Zen Chen, Tainan (TW); Yen-Jou Wu, Tainan (TW); and Yung-Lung Yang, Chiayi (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 31, 2021, as Appl. No. 17/446,585.
Prior Publication US 2023/0062401 A1, Mar. 2, 2023
Int. Cl. H01L 21/66 (2006.01); H10B 41/30 (2023.01); H10B 41/40 (2023.01)
CPC H01L 22/34 (2013.01) [H10B 41/30 (2023.02); H10B 41/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a test region including a test memory cell structure, the test memory cell structure including:
a first gate stack on a first raised portion of a substrate, wherein the first gate stack comprises a first dielectric material, a first polysilicon material above the first dielectric material, and one or more additional dielectric materials above the first polysilicon material,
a first polysilicon structure on a side of the first raised portion and in a region between the side of the first raised portion and a side of a second raised portion of the substrate, wherein no other raised portions are between the first raised portion and the second raised portion,
a first spacer adjacent to on a side of the first polysilicon structure in the region between the side of the first raised portion and the side of the second raised portion,
a second gate stack on the second raised portion, wherein the second gate stack comprises a second dielectric material, a second polysilicon material above the second dielectric material, and one or more other dielectric materials above the second polysilicon material,
a second polysilicon structure on the side of the second raised portion and in the region between the side of the first raised portion and the side of the second raised portion, and
a second spacer on a side of the second polysilicon structure in the region between the side of the first raised portion and the side of the second raised portion; and
an interlayer dielectric (ILD) layer over at least a portion of the test region.