US 12,444,659 B2
Semiconductor device with test pattern structures
Nozomi Kojima, Shiga (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jan. 26, 2022, as Appl. No. 17/585,405.
Prior Publication US 2023/0238292 A1, Jul. 27, 2023
Int. Cl. H01L 21/66 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H01L 22/32 (2013.01) [H01L 21/31116 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory cell region and a peripheral region;
a semiconductor substrate in the memory cell region and the peripheral region;
a dielectric layer on the semiconductor substrate; and
a plurality of test structures on the dielectric layer, the plurality of test structures comprising:
a first test structure including:
a first conductive component and a second conductive component adjacent to one another, the first conductive component comprising a first wiring, and the second conductive component comprising a first contact coupled to the first wiring; and
a second test structure including:
a third conductive component and a fourth conductive component adjacent to one another, the third conductive component comprising a second wiring, and the fourth conductive component comprising a second contact coupled to the second wiring, wherein
a first distance between the first conductive component and the second conductive component is different from a second distance between the third conductive component and the fourth conductive component, and
the first distance is a distance between a side of the first wiring and a side surface of the first contact adjacent to the side of the first wiring, and the second distance is a distance between a side of the second wiring and a side surface of the second contact adjacent to the side of the second wiring.