US 12,444,656 B2
Method for monitoring gate oxide thickness
Haibo Lei, Shanghai (CN); Xingmei Yang, Shanghai (CN); Shenlong Xuan, Shanghai (CN); and Wei Liu, Shanghai (CN)
Assigned to Shanghai Huali Integrated Circuit Corporation, Shanghai (CN)
Filed by Shanghai Huali Integrated Circuit Corporation, Shanghai (CN)
Filed on Jun. 29, 2023, as Appl. No. 18/344,755.
Claims priority of application No. 202211305090.6 (CN), filed on Oct. 24, 2022.
Prior Publication US 2024/0136233 A1, Apr. 25, 2024
Prior Publication US 2024/0234217 A9, Jul. 11, 2024
Int. Cl. H01L 21/66 (2006.01); G01B 7/06 (2006.01)
CPC H01L 22/12 (2013.01) [G01B 7/08 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method for monitoring a gate oxide thickness, comprising at least:
step I. providing a device structure comprising a gate structure, a gate oxide layer under the gate structure, a source region, a drain region, and a base region;
step II. applying an AC voltage on the gate structure, wherein the AC voltage varies in a range from −30 mV−Vdd to +30 mV−Vdd, wherein Vdd is an operating voltage; wherein −Vdd generates an accumulation layer between the source region and the drain region when applied to the gate structure; wherein the source region and the drain region are grounded; and wherein a voltage signal close to 0 potential is applied to the base region;
step III. obtaining a capacitance Cox between the gate structure and the base region according to a capacitance-voltage test method; and
step IV. obtaining the gate oxide thickness of the gate oxide layer according to a formula Tox=ε*S/Cox, where Tox is the gate oxide thickness; ε is a dielectric constant of the gate oxide layer; and S is an area of the gate oxide layer facing a P well.