| CPC H01L 21/76897 (2013.01) [H01L 21/31116 (2013.01); H01L 21/7682 (2013.01); H01L 21/76832 (2013.01); H01L 23/528 (2013.01); H10D 64/017 (2025.01)] | 15 Claims |

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1. A method for fabricating a semiconductor device, comprising:
forming a gate structure on a substrate;
forming a contact etch stop layer (CESL) on the gate structure;
forming an interlayer dielectric (ILD) layer on the CESL;
forming a contact plug in the ILD layer and adjacent to the gate structure;
forming a first stop layer on the ILD layer; and
removing the first stop layer and the ILD layer directly on top of the gate structure and the ILD layer between the CESL and the contact plug to form an air gap exposing the CESL after forming the contact plug.
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