US 12,444,650 B2
Etch stop layer for memory device formation
Sheng-Huang Huang, Hsinchu (TW); Chung-Chiang Min, Zhubei (TW); Harry-Hak-Lay Chuang, Zhubei (TW); Hung Cho Wang, Taipei (TW); and Sheng-Chang Chen, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 20, 2024, as Appl. No. 18/668,329.
Application 18/668,329 is a continuation of application No. 17/843,145, filed on Jun. 17, 2022, granted, now 12,027,420.
Application 17/843,145 is a continuation of application No. 17/007,260, filed on Aug. 31, 2020, granted, now 11,380,580, issued on Jul. 5, 2022.
Claims priority of provisional application 62/927,999, filed on Oct. 30, 2019.
Prior Publication US 2024/0321635 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); G11C 5/06 (2006.01); G11C 11/16 (2006.01); H01L 21/3213 (2006.01); H10N 50/85 (2023.01)
CPC H01L 21/76877 (2013.01) [G11C 5/06 (2013.01); G11C 11/161 (2013.01); H01L 21/3213 (2013.01); H01L 21/76802 (2013.01); H10N 50/85 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
an inter-level dielectric (ILD) laterally surrounding a memory device;
one or more sidewall spacers arranged along opposing sides of the memory device, wherein the one or more sidewall spacers have a bottom surface over a bottom of the memory device;
an etch stop layer disposed on the one or more sidewall spacers and along the opposing sides of the memory device; and
an upper interconnect arranged directly over the memory device, a top surface of the one or more sidewall spacers, and an upper surface of the etch stop layer, the upper surface of the etch stop layer being vertically below a top of the memory device.