US 12,444,647 B2
Electron migration control in interconnect structures
Chun-Jen Chen, Hsinchu (TW); Kai-Shiung Hsu, Hsinchu (TW); Ding-I Liu, Hsinchu (TW); and Jyh-nan Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/227,726.
Application 18/227,726 is a continuation of application No. 17/682,823, filed on Feb. 28, 2022.
Application 17/682,823 is a continuation of application No. 16/941,040, filed on Jul. 28, 2020, granted, now 11,264,273, issued on Mar. 1, 2022.
Claims priority of provisional application 62/967,267, filed on Jan. 29, 2020.
Prior Publication US 2023/0377955 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76826 (2013.01) [H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76849 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
11. An interconnect structure, comprising:
an oxide layer;
a nitride layer disposed on the oxide layer;
a stack of diffusion barrier layers disposed on the nitride layer;
a stack of etch stop layers disposed on the stack of diffusion barrier layers; and
a liner-free conductive structure disposed in the oxide layer and the nitride layer.