US 12,444,646 B2
Devices with reduced capacitances
Yu-Hsin Chan, Hsinchu (TW); Cai-Ling Wu, Hsinchu (TW); Chang-Wen Chen, Hsinchu (TW); Po-Hsiang Huang, Taipei (TW); Yu-Yu Chen, Hsinchu (TW); Kuan-Wei Huang, Taoyuan County (TW); Jr-Hung Li, Hsinchu County (TW); Jay Chiu, Hsinchu (TW); and Ting-Kui Chang, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/446,217.
Application 18/446,217 is a division of application No. 17/382,873, filed on Jul. 22, 2021.
Claims priority of provisional application 63/185,694, filed on May 7, 2021.
Prior Publication US 2024/0021468 A1, Jan. 18, 2024
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H10D 64/23 (2025.01)
CPC H01L 21/7682 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76834 (2013.01); H01L 21/7684 (2013.01); H01L 21/76843 (2013.01); H01L 21/7685 (2013.01); H01L 21/76852 (2013.01); H01L 21/7688 (2013.01); H01L 21/76885 (2013.01); H01L 23/5222 (2013.01); H01L 23/53295 (2013.01); H10D 64/251 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a via structure disposed in a first dielectric layer;
a first etch stop layer (ESL) over the first dielectric layer;
a second dielectric layer over the first ESL;
a diffusion barrier layer extending through the second dielectric layer and the first ESL to contact the via structure;
a metal feature disposed over the diffusion barrier layer;
a protecting layer disposed between the second dielectric layer and the diffusion barrier layer;
a capping layer disposed on top surfaces of the diffusion barrier layer and the metal feature; and
a second ESL over and interfacing the capping layer, the protecting layer and the second dielectric layer,
wherein the second dielectric layer comprises an air gap,
wherein the protecting layer partially extends into the first ESL.