| CPC H01L 21/76232 (2013.01) [H01L 21/0259 (2013.01); H01L 21/3065 (2013.01); H01L 21/308 (2013.01); H10D 30/024 (2025.01); H10D 30/031 (2025.01); H10D 30/6211 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] | 20 Claims |

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1. A method comprising:
forming a first semiconductor layer over a n-type region of a substrate;
forming a second semiconductor layer over a p-type region of the substrate;
performing a first etching process to the first and second semiconductor layers to form a first trench, wherein the first trench has a first inclined surface across an interface between the first and second semiconductor layers;
performing a second etching process to deepen the first trench into a second trench in the substrate, wherein the second trench has a second inclined surface across a boundary between the n-type region and the p-type region;
forming an isolation structure in the second trench; and
forming a gate structure over the isolation structure.
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