| CPC H01L 21/28132 (2013.01) [H01L 21/02326 (2013.01); H01L 21/28114 (2013.01); H01L 21/28518 (2013.01); H01L 21/31116 (2013.01); H01L 21/31155 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6211 (2025.01); H10D 30/797 (2025.01); H10D 62/151 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H10D 64/518 (2025.01); H10D 64/62 (2025.01); H10D 64/671 (2025.01); H10D 84/0135 (2025.01); H10D 84/0147 (2025.01); H10D 84/0172 (2025.01); H10D 84/0184 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A structure comprising:
a gate spacer over a semiconductor substrate, the gate spacer having a first sidewall and a second sidewall opposite the first sidewall, wherein the gate spacer has an upper portion, a lower portion, and a projecting portion extending from the lower portion;
an epitaxial source/drain region adjacent the first sidewall of the gate spacer;
a gate dielectric extending along the second sidewall of the gate spacer and a top surface of the semiconductor substrate, wherein the projecting portion of the gate spacer extends into the gate dielectric;
a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion of the gate electrode increasing continually in a first direction extending away from the top surface of the semiconductor substrate, a second width of the lower portion of the gate electrode being constant along the first direction;
a gate mask over the gate electrode and the gate dielectric, a third width of the gate mask increasing continually in the first direction; and
a gate contact extending through the gate mask to contact the gate electrode.
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9. A structure comprising:
a gate spacer over a semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction;
a gate structure comprising a gate dielectric and a gate electrode on the gate dielectric, the gate dielectric extending along the upper portion of the gate spacer, the lower portion of the gate spacer, and the top surface of the semiconductor substrate, wherein the gate spacer has a projecting portion extending from the lower portion of the gate spacer and into the gate structure, the gate dielectric having a first notch where the projecting portion of the gate spacer extends into the gate dielectric;
a gate mask over the gate structure, the gate mask extending along the upper portion of the gate spacer; and
an epitaxial source/drain region, wherein adjacent a second sidewall of the gate spacer is disposed between the epitaxial source/drain region and the gate structure.
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13. A structure comprising:
an isolation region;
a semiconductor fin protruding above the isolation region;
a gate structure extending along a sidewall of the semiconductor fin and along a top surface of the isolation region, an upper portion of the gate structure having slanted sidewalls, a lower portion of the gate structure having parallel sidewalls, the gate structure comprising a gate dielectric and a gate electrode on the gate dielectric;
a gate mask over the gate structure, the gate mask having slanted sidewalls; and
gate spacers extending along the parallel sidewalls of the lower portion of the gate structure, along the slanted sidewalls of the upper portion of the gate structure, and along the slanted sidewalls of the gate mask, wherein the gate spacers include projecting portions extending into the gate structure, the gate dielectric having first notches where the projecting portions of the gate spacers extend into the gate dielectric, the gate electrode having second notches where the first notches of the gate dielectric extend into the gate electrode.
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