US 12,444,600 B2
Gallium nitride device having a combination of surface passivation layers
Dong Seup Lee, McKinney, TX (US); Jungwoo Joh, Allen, TX (US); and Yoshikazu Kondo, Sachse, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Sep. 30, 2021, as Appl. No. 17/491,185.
Prior Publication US 2023/0094094 A1, Mar. 30, 2023
Int. Cl. H01L 21/02 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01)
CPC H01L 21/022 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02271 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01)] 25 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, the method comprising:
providing a gallium nitride (GaN) substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate; and
forming a composite surface passivation layer over the epitaxial layer, the composite surface passivation layer comprising a first passivation layer portion formed at a first region of the semiconductor device and a second passivation layer portion formed at a second region of the semiconductor device, wherein the first passivation layer portion is formed as part of a first process and the second passivation layer portion is formed as part of a second process, wherein
the first passivation layer portion is formed proximate to a drain access region of the semiconductor device, the first passivation layer portion comprising a first dielectric material deposited in the first process involving a lower O2 environment than the second process.