US 12,444,598 B2
Gate structure fabrication techniques for reducing gate structure warpage
Chandrashekhar Prakash Savant, Hsinchu (TW); Kin Shun Chong, Hsinchu (TW); Tien-Wei Yu, Hsinchu (TW); and Chia-Ming Tsai, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 26, 2022, as Appl. No. 17/825,798.
Claims priority of provisional application 63/282,777, filed on Nov. 24, 2021.
Prior Publication US 2023/0162973 A1, May 25, 2023
Int. Cl. H01L 21/02 (2006.01); C23C 16/02 (2006.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01); H10D 84/83 (2025.01)
CPC H01L 21/0217 (2013.01) [H01L 21/02274 (2013.01); H10D 30/024 (2025.01); H10D 64/017 (2025.01); H10D 84/834 (2025.01); C23C 16/0245 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a gate stack, the method comprising:
depositing a gate dielectric layer on a channel region;
depositing a work function layer on the gate dielectric layer;
forming a stress-treated glue layer on the work function layer, wherein the forming the stress-treated glue layer includes a deposition process and a stress reduction treatment process, wherein the deposition process includes:
depositing a first glue sublayer over the work function layer,
depositing a metal layer over the first glue sublayer, and
depositing a second glue sublayer over the metal layer; and
the stress reduction treatment process includes performing a hydrogen poisoning treatment; and
depositing a metal fill layer on the stress-treated glue layer.