US 12,444,475 B2
Reducing read error handling operations during power up of a memory device
Dongxiang Liao, Cupertino, CA (US); and Tomer Tzvi Eliash, Sunnyvale, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 2, 2024, as Appl. No. 18/431,279.
Claims priority of provisional application 63/486,856, filed on Feb. 24, 2023.
Prior Publication US 2024/0290413 A1, Aug. 29, 2024
Int. Cl. G11C 29/44 (2006.01); G11C 16/28 (2006.01)
CPC G11C 29/44 (2013.01) [G11C 16/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
maintaining a boot-up read pattern data structure, wherein each entry of the boot-up read pattern data structure comprises a boot-up read pattern represented as a plurality of logical block addresses (LBAs) that were read during a respective power cycle event and a dummy boot-up read pattern flag;
for each power cycle event, storing, in a new entry of the boot-up read pattern data structure, a current boot-up read pattern associated with a respective power cycle event;
comparing the current boot-up read pattern with a previous boot-up read pattern associated with a latest entry of the boot-up pattern data structure; and
responsive to the comparing the current boot-up read pattern and the previous boot-up read pattern, updating a dummy boot-up read pattern flag of the new entry, wherein the dummy boot-up read pattern flag indicates that the current boot-up read pattern and the previous boot-up pattern are the same boot-up pattern that has been consecutively used during boot up.