US 12,444,474 B2
Voltage ramp memory calibration
Robert E. Jeter, Santa Clara, CA (US); Jingkui Zheng, Sunnyvale, CA (US); and Srinivasa Rao Masanam, Cedar Park, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Nov. 30, 2023, as Appl. No. 18/525,088.
Claims priority of provisional application 63/584,429, filed on Sep. 21, 2023.
Prior Publication US 2025/0104790 A1, Mar. 27, 2025
Int. Cl. G11C 7/22 (2006.01); G11C 29/12 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/12015 (2013.01) [G11C 7/222 (2013.01); G11C 29/1201 (2013.01); G11C 29/46 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory controller circuit, wherein the memory controller circuit is configured to convey a clock signal to a memory, wherein the memory controller circuit includes:
a calibration control circuit configured to perform a plurality of calibrations of the clock signal during a change from a first one of a plurality of performance states to a second one of the plurality of performance states; and
a delay circuit configured to apply a delay to and convey the clock signal to the memory;
wherein, in performing a given one of the plurality of calibrations, the calibration control circuit is configured to:
convey, to the memory, a first command to begin a timing test that generates a count value indicative of a current voltage of the memory;
receive the count value from the memory at a conclusion of the timing test; and
cause the delay circuit to adjust, based on the count value, the delay applied to the clock signal.