US 12,444,473 B2
Shift register unit and display panel
Yao Huang, Beijing (CN); Xilei Cao, Beijing (CN); and Zhenhua Zhang, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., Beijing (CN)
Appl. No. 18/291,927
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Chengdu (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed May 20, 2022, PCT No. PCT/CN2022/094154
§ 371(c)(1), (2) Date Jan. 25, 2024,
PCT Pub. No. WO2023/221102, PCT Pub. Date Nov. 23, 2023.
Prior Publication US 2024/0249786 A1, Jul. 25, 2024
Int. Cl. G11C 19/28 (2006.01); G09G 3/20 (2006.01)
CPC G11C 19/28 (2013.01) [G09G 3/20 (2013.01); G09G 2310/0286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register unit, comprising:
an input circuit, connected to a first signal input terminal, a second signal input terminal and a first node and receiving a first level signal, wherein the input circuit is configured to transmit a signal of the first signal input terminal to the first node in response to the signal of the first signal input terminal and transmit the first level signal to the first node in response to a signal of the second signal input terminal;
a first control sub-circuit, connected to the first node, a second node and a clock signal terminal and receiving the first level signal, wherein the first control sub-circuit is configured to periodically transmit the received first level signal to the first node in response to a turned-on signal of the second node and a periodic clock signal of the clock signal terminal;
a first output sub-circuit, connected to the first node, the clock signal terminal and a signal output terminal, wherein the first output sub-circuit is configured to transmit the signal of the clock signal terminal to the signal output terminal in response to a signal of the first node.