US 12,444,469 B2
NAND flash memory device capable of selectively erasing one flash memory cell and operation method thereof
Honam Yoo, Icheon (KR); and Jong-Ho Lee, Seoul (KR)
Assigned to SK hynix Inc., Icheon (KR); and Seoul National University R&DB Foundation, Seoul (KR)
Filed by SK hynix Inc., Icheon (KR); and Seoul National University R&DB Foundation, Seoul (KR)
Filed on Apr. 7, 2022, as Appl. No. 17/715,809.
Claims priority of provisional application 63/271,926, filed on Oct. 26, 2021.
Claims priority of application No. 10-2021-0182231 (KR), filed on Dec. 17, 2021.
Prior Publication US 2023/0128347 A1, Apr. 27, 2023
Int. Cl. G11C 16/16 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/107 (2013.01); G11C 16/24 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A flash memory device comprising:
a cell array including a first NAND string having a plurality of first flash memory cells having control gates connected to a plurality of word lines, respectively, and a first bit line selection switch connecting the plurality of first flash memory cells to a first bit line according to a control of a first string selection line; and
a control circuit configured to control a first erase operation for erasing a selected flash memory cell among the plurality of first memory cells,
wherein the control circuit controls a voltage difference between the first bit line and the first string selection line to have a first value for generating gate induced drain leakage (GIDL) at the first bit line selection switch, and controls a voltage of a control gate of the selected flash memory cell and a voltage of a control gate of an unselected flash memory cell among the plurality of first flash memory cells to be different from each other,
wherein the cell array further comprises a second NAND string having a plurality of second flash memory cells having control gates connected to the plurality of word lines, respectively, and a second bit line selection switch connecting the plurality of second flash memory cells to the first bit line according to a control of a second string selection line, and
wherein the control circuit controls a voltage difference between the first bit line and the second string selection line to have a second value that is smaller than the first value during the first erase operation.