| CPC G11C 16/08 (2013.01) [G11C 5/063 (2013.01); G11C 16/0483 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
|
1. A memory device comprising:
a plurality of memory planes that each includes a memory cell array including a plurality of non-volatile memory cells, a row decoder array connected to the plurality of non-volatile memory cells included in the memory cell array through a plurality of word lines extending in a first horizontal direction, and a page buffer array connected to the plurality of non-volatile memory cells included in the memory cell array through a plurality of bit lines extending in a second horizontal direction crossing the first horizontal direction;
a peripheral circuit structure including the row decoder array included in each of the plurality of memory planes and the page buffer array included in each of the plurality of memory planes; and
a cell array structure on the peripheral circuit structure, the cell array structure overlapping the peripheral circuit structure in a vertical direction on the peripheral circuit structure, wherein the cell array structure includes the memory cell array of each of the plurality of memory planes, and a word line step region in which the plurality of word lines extend parallel to each other in the first horizontal direction and the second horizontal direction and overlap each other in the vertical direction,
wherein, in each of the plurality of memory planes, the page buffer array is divided into a page buffer array connected to bit lines of a partial region of the memory cell array that overlaps a part of the row decoder array in the vertical direction and a page buffer array connected to other bit lines not included in the partial region.
|