| CPC G11C 16/0483 (2013.01) [H01L 23/5283 (2013.01); H01L 24/48 (2013.01); H10B 41/30 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 30/6755 (2025.01); H01L 2224/73265 (2013.01); H01L 2924/00 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/181 (2013.01); H10B 41/10 (2023.02); H10B 69/00 (2023.02)] | 18 Claims |

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1. A memory device comprising:
a first conductor;
a second conductor above the first conductor;
a third conductor above the second conductor;
a fourth conductor above the third conductor;
a fifth conductor above the fourth conductor;
a sixth conductor above the fifth conductor;
a seventh conductor;
a first insulator;
a second insulator;
a first semiconductor; and
a second semiconductor,
wherein an opening is provided through at least the second conductor, the third conductor, the fourth conductor, the fifth conductor, and the sixth conductor and reaches a top surface of the first conductor,
wherein the first insulator, the first semiconductor, the seventh conductor, the second insulator, and the second semiconductor are provided in this order from an outside in a first region of the opening that overlaps with the third conductor,
wherein the first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order from the outside in a second region of the opening that overlaps with the fourth conductor,
wherein the first semiconductor comprises a first portion in direct contact with a top surface of the second conductor and a second portion in direct contact with a side surface of the fifth conductor, and
wherein the second semiconductor comprises a first portion in direct contact with the top surface of the first conductor and a second portion in direct contact with a side surface of the sixth conductor.
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