| CPC G11C 16/0483 (2013.01) [H10B 41/10 (2023.02); H10B 41/27 (2023.02)] | 16 Claims |
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1. A memory device, comprising:
a stacked structure comprising conductive layers;
a lower isolation structure in the stacked structure and having an upper surface in a lower portion of the stacked structure, wherein the lower isolation structure separates at least one conductive layer of the conductive layers into a first conductive strip and a second conductive strip, the first conductive strip and the second conductive strip are electrically isolated from each other;
two memory strings in the stacked structure and electrically connected to the first conductive strip and the second conductive strip respectively;
isolation elements in the stacked structure; and
blocks separated from each other by the isolation elements, wherein the lower isolation structure is in one of the blocks between two adjacent isolation elements of the isolation elements.
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