US 12,444,464 B2
Resistive memory device and method of operating the resistive memory device
In Ku Kang, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Sep. 15, 2023, as Appl. No. 18/468,500.
Application 18/468,500 is a continuation of application No. 17/530,998, filed on Nov. 19, 2021, granted, now 11,804,265.
Claims priority of application No. 10-2021-0081963 (KR), filed on Jun. 24, 2021.
Prior Publication US 2024/0005989 A1, Jan. 4, 2024
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01); G11C 13/0097 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A resistive memory device, comprising:
strings respectively coupled between source lines and bit lines, wherein the strings include source select transistors respectively coupled to the source lines, drain select transistors respectively coupled to the bit lines, and resistive memory cells between the drain select transistors and the source select transistors;
word lines coupled to the resistive memory cells;
a source select line coupled to the source select transistors;
a drain select line coupled to the drain select transistors;
page buffers configured to selectively apply a set voltage to bit lines coupled to selected resistive memory cells among the resistive memory cells; and
a voltage generator configured to control a level of a turn-on voltage applied to the source select line depending on a program target state of the selected resistive memory cells.