| CPC G11C 11/4099 (2013.01) [G11C 11/4091 (2013.01); G11C 11/4094 (2013.01)] | 20 Claims |
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1. A static random access memory (SRAM) comprising:
a memory cell configured to store data;
a reference voltage generator comprising a reference voltage generation circuit configured to generate a reference voltage based on voltage division and a reference voltage trimming circuit configured to trim a value of the reference voltage;
a precharge circuit connected with the memory cell through a bit line, connected with the reference voltage generator through a reference bit line, and configured to pre-charge the bit line and the reference bit line; and
a sense amplifier connected with the bit line and the reference bit line, and configured to compare a voltage of the bit line and a voltage of the reference bit line and to determine a value of the data stored in the memory cell based on a result of the compare,
wherein the reference voltage generation circuit comprises a first p-channel metal-oxide semiconductor (PMOS) transistor connected between a terminal providing a power supply voltage and a first node from which the reference voltage is output, and
each of the reference voltage generation circuit and the reference voltage trimming circuit comprises another PMOS transistor connected to the first node and configured to operate in response to a same reference voltage enable signal.
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