US 12,444,460 B2
Memory device, electronic device, and operation method of memory device
Minsu Jung, Suwon-si (KR); Jindo Byun, Suwon-si (KR); Joohwan Kim, Suwon-si (KR); Eun Seok Shin, Suwon-si (KR); Hyun-Yoon Cho, Suwon-si (KR); and Junghwan Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 15, 2023, as Appl. No. 18/541,218.
Claims priority of application No. 10-2022-0185047 (KR), filed on Dec. 26, 2022.
Prior Publication US 2024/0212746 A1, Jun. 27, 2024
Int. Cl. G11C 11/40 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); H03K 19/017 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4093 (2013.01); H03K 19/01742 (2013.01); G11C 2207/2254 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a pull-up driver connected between a power supply voltage and a first node;
a T-coil circuit connected between the first node and a second node;
an external resistor; and
a ZQ controller configured to perform a ZQ calibration operation on the pull-up driver,
wherein the ZQ controller comprises:
a path selecting circuit configured to select one node among the first node and the second node;
a comparing circuit configured to:
compare a voltage of the one node selected by the path selecting circuit with a pull-up reference voltage, and
output a comparison result based the comparison between the voltage of the one node selected by the path selecting circuit and the pull-up reference voltage; and
a code generating circuit configured to generate a pull-up code for driving the pull-up driver, based on the comparison result, and
wherein, while the pull-up code is generated, the external resistor is connected between the second node and a ground voltage.