US 12,444,458 B2
Memory cell array of a static random access memory and a static random access memory including the same
Hyunjun Kim, Suwon-si (KR); Sekeon Kim, Seoul (KR); Seongook Jung, Seoul (KR); Kyeongrim Baek, Seoul (KR); and Keonhee Cho, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 28, 2023, as Appl. No. 18/227,355.
Claims priority of application No. 10-2023-0003326 (KR), filed on Jan. 10, 2023.
Prior Publication US 2024/0233812 A1, Jul. 11, 2024
Int. Cl. G11C 11/4096 (2006.01); G11C 5/06 (2006.01); G11C 11/4074 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 5/063 (2013.01); G11C 11/4074 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory cell array of a static random access memory (SRAM) comprising:
a top memory cell array including a plurality of top memory cells; and
a bottom memory cell array including a plurality of bottom memory cells,
wherein the plurality of top memory cells include:
a first top memory cell connected between a power supply voltage and a middle node, and connected to a first top wordline, a first top bitline and a first top complementary bitline,
wherein the plurality of bottom memory cells include:
a first bottom memory cell configured to operate with the first top memory cell, connected between the middle node and a ground voltage, and connected to a first bottom wordline, a first bottom bitline and a first bottom complementary bitline, and
wherein, when a write operation and a read operation are not performed on the first top memory cell and the first bottom memory cell, the first top bitline, the first top complementary bitline, the first bottom bitline and the first bottom complementary bitline are electrically connected to the middle node, and
wherein the first bottom memory cell is configured to be supplied with a power from the power supply voltage middle node.