| CPC G11C 11/4093 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); H01L 25/18 (2013.01)] | 20 Claims |
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1. A memory device comprising:
a logic die configured to communicate with a host device through a plurality of channels, each of which including an independent interface; and
a plurality of memory dies stacked on the logic die, each of the plurality of memory dies including a memory cell array corresponding to at least one of the plurality of channels,
wherein the logic die includes:
first pins configured to receive a clock signal having a first clock frequency;
second pins configured to receive a write command/address signal based on the clock signal;
third pins configured to receive a write strobe signal having a second clock frequency; and
DQ pins configured to receive a write data signal based on a plurality of internal write data strobe signal, the plurality of internal write data strobe signal being based on write strobe signal,
wherein the first clock frequency is half of the second clock frequency,
wherein the write strobe signal includes a main toggling period aligned with the write data signal,
wherein a number of write pre-amble cycles of the write strobe signal before the main toggling period is even-numbered, and
wherein a number of write post-amble cycles of the write strobe signal after the main toggling period is even-numbered.
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