US 12,444,455 B2
Memory structure
Yifei Yan, Quanzhou (CN); Hui-Huang Chen, Quanzhou (CN); and Chao-Wei Lin, Quanzhou (CN)
Assigned to Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed by Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed on Oct. 4, 2023, as Appl. No. 18/376,455.
Claims priority of application No. 202310661380.2 (CN), filed on Jun. 6, 2023; and application No. 202321421522.X (CN), filed on Jun. 6, 2023.
Prior Publication US 2024/0412772 A1, Dec. 12, 2024
Int. Cl. G11C 11/408 (2006.01); G11C 5/06 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/4085 (2013.01) [G11C 5/063 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10B 12/50 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A memory structure, comprising:
a substrate;
a first device layer disposed on the substrate;
a plurality of memory regions in the first device layer;
a plurality of word lines and bit lines in the first device layer to control memory cells of the memory regions;
a second device layer disposed between the substrate and the first device layer; and
a plurality of first peripheral regions and second peripheral regions alternately arranged in the second device layer, wherein in a top view, the first peripheral regions and the second peripheral regions respectively partially overlap adjacent two of the memory regions, wherein odd rows of the bit lines are electrically connected to the first peripheral regions, and even rows of the bit lines are electrically connected to the second peripheral regions.