US 12,444,453 B2
Volatile data storage in NAND memory
Jeffrey S. McNeil, Nampa, ID (US); Eric N. Lee, San Jose, CA (US); Tomoko Ogura Iwasaki, San Jose, CA (US); Sheyang Ning, San Jose, CA (US); Lawrence Celso Miranda, San Jose, CA (US); and Kishore Kumar Muchherla, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Nov. 8, 2023, as Appl. No. 18/388,032.
Claims priority of provisional application 63/428,755, filed on Nov. 30, 2022.
Prior Publication US 2024/0177755 A1, May 30, 2024
Int. Cl. G11C 16/04 (2006.01); G06F 12/02 (2006.01); G11C 11/00 (2006.01)
CPC G11C 11/005 (2013.01) [G06F 12/0246 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause to memory to:
access a first string of series-connected memory cells of the plurality of strings of series-connected memory cells in a first mode of operation for volatile storage of data to the first string of series-connected memory cells; and
access a second string of series-connected memory cells of the plurality of strings of series-connected memory cells in a second mode of operation for non-volatile storage of respective data to each memory cell of a plurality of memory cells of the second string of series-connected memory cells.