US 12,444,452 B2
Memory physical layer interface, memory apparatus and method thereof
Sivaramakrishnan Subramanian, Bengaluru (IN); Hussainvali Shaik, Bangalore (IN); and Eswar Reddi, Bangalore (IN)
Assigned to Faraday Technology Corp., Hsinchu (TW)
Filed by Faraday Technology Corp., Hsinchu (TW)
Filed on Nov. 15, 2023, as Appl. No. 18/509,318.
Prior Publication US 2025/0157515 A1, May 15, 2025
Int. Cl. G11C 8/18 (2006.01); G11C 7/10 (2006.01); G11C 7/20 (2006.01); G11C 7/22 (2006.01)
CPC G11C 8/18 (2013.01) [G11C 7/1069 (2013.01); G11C 7/20 (2013.01); G11C 7/222 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
a memory device;
a memory controller; and
a memory physical layer interface, coupled between the memory device and the memory controller, the memory physical layer interface comprises:
a decision feedback equalization (DFE) receiver, receiving a data signal and a data strobe signal from the memory device, wherein the DFE receiver comprises a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap; and
a DFE reset circuit, receiving a gate enable signal and an internal enable signal from the memory controller, generating a DFE reset signal according to the gate enable signal and the internal enable signal, and outputting the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.