| CPC G11C 7/222 (2013.01) [G11C 7/1012 (2013.01); G11C 7/1066 (2013.01)] | 20 Claims |
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1. A memory interface circuit comprising:
a first receiver coupled to a differential data strobe signal that is received from a memory device and that comprises a pair of complementary signals;
a second receiver having a first input coupled to a reference voltage source and a second input coupled to one of the pair of complementary signals;
a qualification circuit configured to:
detect a preamble transmission in the differential data strobe signal based on timing provided by an output of the first receiver when the memory interface circuit is in a first operating state,
detect the preamble transmission in the differential data strobe signal based on timing provided by an output of the second receiver when the memory interface circuit is in a second operating state, and
assert a preamble detection signal when the preamble transmission is detected; and
a gating circuit configured to provide a receive clock signal representative of the differential data strobe signal when the preamble detection signal is asserted.
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